1. Field of the Invention
This invention is concerned with synchronization of peripheral devices in a multi-microprocessor implemented data processing system that emulates a mainframe system. More particularly, this invention is directed to optimizing the performance of such a system insofar as peripheral synchronization without device polling is concerned.
2. Description of the Prior Art
The emulation of "mainframe" data processing systems through the use of microprocessors has become a reality. A typical main frame data processing system would be any one of the System/370 (S/370) models available from International Business Machines Corporation. The Personal Computer XT/370, a "desktop" System/370, also available from International Business Machines Corporation, is one example of such a microprocessor implemented main frame. This particular desktop system is a hardware/software package that allows one to run System/370 application programs in a single user environment, to run as a terminal attached to a main frame host or to run in a stand-alone mode as a personal computer, as required by the particular application. There are, of course, similar systems available from other manufacturers, all of which systems incorporate many of the same functions as the Personal Computer XT/370 although the manner and means of implementation does differ, in varying degrees, from system to system.
Due to revolutionary advances in chip densities and packaging, which have been accompanied by significant reductions in costs, many main frame features can now be implemented directly in a desktop system, while other features require some hardware and/or software assistance in order to make them available. The introduction and use of more powerful microprocessors such as, for example, the 8086 and 8088 from Intel Corporation and the 68000 from Motorola Corporation, added further to the list of functions it would be possible to implement in a desktop mainframe. This new breed of microprocessors is fully capable of running a large, enriched instruction set, such as that of System/370, although several of these microprocessors, working in concert with the aid of additional hardware and/or software support, would be required to effect instruction execution in an acceptable time period. It will also be appreciated that presently available microprocessors, while remarkable for the functions they do offer, are not capable of providing all mainframe capability without system compromise.
Thus, as in all data processing system designs, various trade-offs are made in order to optimize the price and performance of these microprocessor implemented desktop mainframes. One particular trade-off problem is posed by the need or desire to utilize certain mainframe functions and features that would be particularly difficult to provide in a microprocessor implemented desktop mainframe. Another type of trade-off problem is posed by the requirement that all architectural constraints of the emulated mainframe be adhered to so that user programs can be run without concern. One specific implementation problem of concern, due in part to such trade-offs being made, is that of synchronizing the operation of the microprocessor in control or host processor with that of a peripheral device.
Typically, this task is handled by having the host processor access a peripheral, poll its status bits to determine when the peripheral has completed its operation and read any resulting information. The polling function is generally implemented by a microcode loop which reads the status bits of the peripheral being used and then branches, if appropriate, on the results. However, this approach has several drawbacks, particularly in a microprocessor implemented system.
The polling microcode is extra code that must be written and debugged. For performance purposes, the polling microcode is generally resident in the host processor's control store. Thus, it is essential that the microcode be error free since it is virtually impossible to change or patch. In addition, in a microprocessor implemented system, the polling microcode would be permanently loaded into the processor's on-chip control store, which represents a very limited and valuable system resource that could be put to other functional use. In fact, the control storage space taken by polling microcode prevents the use of that space for other code that might have a more beneficial impact on system performance.
The use of polling logic and support therefor may also incur a performance penalty in the system. The processor must execute a loop to constantly monitor the status of the peripheral device in which it is interested. This loop requires a bus cycle to read the peripheral's status bits and a number of internal operations to determine if peripheral access is complete. With the host processor in a microcode loop, if completion of peripheral operation occurs just after its status bits are read, detection of this fact will be delayed until the next loop iteration. Hence, each time a peripheral is accessed, the time required to execute a single loop may be added to the total access time for a particular peripheral. In a microprocessor implemented mainframe, this can result in system performance degradation if the peripheral is a high usage device. Thus, while it would be possible to utilize microcode implemented peripheral synchronization via polling in a microprocessor implemented mainframe data processing system, the performance and/or control storage penalties associated with that solution to the problem are not acceptable.